1. Field
Example embodiments relate to a method of reading data in a memory device. Also, example embodiments relate to a method and apparatus for reading data in a multi-level cell (MLC) or multi-bit cell (MBC) memory device.
2. Description of Related Art
A single-level cell (SLC) memory device may store one bit of data in a single memory cell. The SLC memory may be referred to as a single-bit cell (SBC) memory. The SLC memory may store and read data of one bit at a voltage level included in two distributions that may be divided by a threshold voltage level programmed in a memory cell. Due to a fine electrical characteristic difference between SLC memories, the programmed threshold voltage level may have the distribution within a predetermined range. For example, when a voltage level read from the memory cell is greater than 0.5V and less than 1.5V, it may be determined that the data stored in the memory cell has a logic value of “1”. When the voltage level read from the memory cell is greater than 2.5V and less than 3.5V, it may be determined that the data stored in the memory cell has a logic value of “0”. The data stored in the memory cell may be classified depending on the difference between cell currents and/or cell voltages during the reading operations.
Meanwhile, a multi-level cell (MLC) memory device that can store data of two or more bits in a single memory cell has been proposed in response to a need for higher integration of memory. The MLC memory device may also be referred to as a multi-bit cell (MBC) memory. However, as the number of bits stored in the single memory cell increases, reliability may deteriorate and the read-failure rate may increase. To store ‘m’ bits in a single memory cell, a single threshold voltage level may be formed in the single memory cell from among 2m threshold voltage levels. Due to a fine electrical characteristic difference between memory cells of MLC memories, when storing ‘m’ bits in each of the memory cells of the MLC memories, threshold voltage levels formed in the memory cells of the MLC memories may form 2m distributions.
The number of distributions of threshold voltage levels in a voltage window may increase in proportion to 2m as ‘m’ increases. A voltage window of a memory may be limited. Accordingly, when the distance between adjacent distributions decreases or distributions are overlapped due to the increase in ‘m’, the read-failure rate of data stored in a memory may increase. For this reason, it may be difficult to improve storage density using a MLC memory device.
With the current increase in the utilization of the MLC memory device, error correction codes or error control codes (ECC) that may detect an error during data storing and reading operations and correct the detected error are may be more widely used. As an error correcting capability of ECC increases, hardware complexity of an ECC decoder may increase.